A Review on Parallel LDPC Decoder Architecture

Low Density Parity Check (LDPC) codes offer excellent error correcting performance and is being widely considered in next generation industry standards. The main challenge with implementing Parallel Decoder Architecture for LDPC codes is the interconnection of the functional units at the top level. For applications that require high throughput and low power dissipation and tolerate a fixed code format and large area, the Parallel Architecture is very suitable. The proposed Parallel Decoder Architecture supports a maximum Throughput with improved Bit Error Performance and provides Girth Optimization with simple interconnection.